9. Document Revision History for the H-Tile Hard IP for Ethernet...

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683430

Date 5/03/2024

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9. Document Revision History for the H-Tile Hard IP for Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

Document Version	Quartus® Prime Version	IP Version	Changes
2024.05.03	24.1	19.6.0	Changed Nios® II to Nios® V in IP Core Generated Files table of the Generated File Structure topic.
2024.04.09	21.1	19.3.0	Updated the Stratix® 10 device family support to Final in Table: H-Tile Hard IP for Ethernet Device Family Support. Updated the note about the OTN feature.
2024.01.18	21.1	19.3.0	Updated Enable TX Pause Ports topic in Pause and Priority- Based Flow Control Registers section. Updated `en_pfc_port` register access to RW in Enable TX Pause Ports.
2023.09.06	21.1	19.3.0	Updated BER count description in the BER Count register.
2022.02.16	21.1	19.3.0	Added "IP-ETH-HTILEKRCR" to Ordering Codes to enable KR/CR (AN/LT)
2021.08.27	21.1	19.3.0	Revised Transceiver Reconfiguration Signals: Corrected description in the Writing to Transceiver Reconfiguration CSRs through Transceiver Avalon Memory-Mapped (MM) Interface table. Corrected description in the Reading from Transceiver Reconfiguration CSRs through Transceiver Avalon Memory-Mapped (MM) Interface table.
2021.06.02	21.1	19.3.0	Removed support for the Agilex™ 7 device family. Updated EHIP TX MAC Feature Configuration Fields by excluding flowreg_rate register details.
2020.12.10	20.3	-	Added support for the Agilex™ 7 device family. Added new section: Ethernet Toolkit Overview Corrected description of the following PHY Registers: Recovered Clock Frequency in KHz TX Clock Frequency in KHz
2020.06.22	20.2	19.3.0	Updated Average Inter-packet Gap description in the H-Tile Hard IP for Ethernet Parameters: IP Tab table and the Inter-Packet Generation and Insertion section. Updated RTL Parameters section to clarify the access to the RTL generated parameters in simulation and synthesis. The 50G Hard IP for Ethernet is no longer available in the Quartus® Prime Pro Edition software. For additional information, contact Intel support.
2019.10.31	19.3	19.2.0	Replaced Altera Debug Master Endpoint (ADME) with Native PHY Debug Master Endpoint (NPDME). Added Enable JTAG to Avalon Master Bridge parameter in the Parameter Editor Parameters section. Updated Release Information section: Added IP versioning description Updated release information Updated ordering code from IP-ETH-HTILEHARDIP to IP-ETH-HTILEHIP Added section Disabling Background Calibration to clarify support for Auto adaptation triggering for RX PMA CTLE/DFE mode. Removed RS-FEC from the TX PCS Datapath and RX PCS Datapath figures. RS-FEC is not supported in the H-Tile Hard IP for Ethernet IP. Updated System Consideration by including the `i_reconfig_reset` signal in the system reset operation. In PLL Configuration Example for 100GBASE-R4 (Synchronous Mode) IP Core Variation figure, added arrow between the Main ATX PLL block and ATX PLL (Clock Buffer) block. Added TX Avalon-ST MAC Client Interface for H-Tile Hard IP for Ethernet IP Core with `readyLatency` = 3 figure in the TX MAC Interface to User Logic section.
2019.02.12	18.1	18.1	Corrected the signal width error for the `i_eth_reconfig_addr` signal in the Interfaces and Signal Descriptions and Ethernet Reconfiguration Interface sections. The correct width is 16 bits, not 12 bits.
2019.01.21	18.1	18.1	Created chapters for MAC and PCS interfaces: H-tile Hard IP for Ethernet Intel FPGA MAC Interface H-tile Hard IP for Ethernet Intel FPGA PCS Only/PCS66 Interface Renamed the Soft eHIP Reset Sequencer and KR Reset Controller block to KR Soft Reset Sequencer and Controller in the H-tile Hard IP for Ethernet FPGA IP block diagram for better clarity. Edited the note about generating transceiver PLLs in the Adding the Transceiver PLLs section to clarify that you need to generate ATX PLL IP cores to connect in your design if it includes multiple instances of the H-tile Hard IP for Ethernet FPGA IP. Corrected the PLL signal name from `tx_serial_clk` to `tx_serial_clk_gxt` in the Adding the Transceiver PLLs section. Updated the descriptions for the following registers: ANLT Sequencer Status Auto Negotiation Status Register Auto Negotiation Config Register 3 Link Training Config Register 1 Link Training Status Register 1 Local Link Training Parameters
2018.08.10	18.0	18.0	Added a note to clarify that the H-Tile Hard IP for Ethernet IP provides preliminary support for the OTN feature in the following sections: About the H-Tile Hard IP for Ethernet IP Core IP Core Supported Features Resource Utilization Parameter Editor Parameters Functional Description FlexE and OTN Mode TX Interface FlexE and OTN Mode RX Interface
2018.07.20	18.0	18.0	Added Functional Description section. Added OTN and FlexE features in the H-Tile Hard IP for Ethernet IP Core Supported Features section. Added Link fault generation option, Enable asynchronous adapter clock, and Enable Altera Debug Master Endpoint (ADME) parameters in the Parameter Editor Parameters section. Added OTN and FlexE variants in the Parameter Editor Parameters section. Added Ethernet Reconfiguration and Status Register Descriptions section. Updated IP Core FPGA Resource Utilization table with resource utilization for: 50-Gbps and 100-Gbps PCS only variants 50-Gbps and 100-Gbps OTN only variants 50-Gbps and 100-Gbps FlexE only variants Updated configuration for transceiver PLLs when using 100-Gbps data rate in 50-Gbps and 100-Gbps MAC + PCS with Auto Negotiation and Link Training variants Adding the Transceiver PLLs topic. Added configuration for transceiver PLLs when using 50-Gbps data in Adding the Transceiver PLLs topic. Added waveform diagrams for: 50-Gbps and 100-Gbps MAC + PCS Alignment marker on TX PCS interface Data transmit on TX FlexE and OTN interfaces Alignment marker on TX FlexE and OTN interfaces Data received on TX FlexE and OTN interfaces Write to/read from transceiver reconfiguration CSRs using Avalon-MM interface Status interface behavior during link startup with and without bidirectional link fault enabled TX and RX datapath reset sequences Added Reset Signal Functions table in Reset topic. Renamed Intel Stratix 10 H-Tile Hard IP for Ethernet to H-tile Hard IP for Ethernet Intel FPGA as per Intel rebranding.
2018.01.12	17.1	17.1	Initial public release. At this time, the Registers and Functional Description chapters are pending.