2.4.3. Adding the Transceiver PLLs

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 4/09/2024

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2.4.3. Adding the Transceiver PLLs

The H-Tile Hard IP for Ethernet IP core requires two TX transceiver PLLs that are not part of the IP core, to compile and to function correctly in hardware. On Stratix® 10 devices, only the ATX PLL supports the required data rate.

The transceiver PLLs you configure are physically present on the device, but the H-Tile Hard IP for Ethernet IP core does not configure and connect them. The required number of ATX PLLs is two for 100GBASE-R4 variations. Each ATX PLL drives the clocks for two transceiver channels.

Figure 5. PLL Configuration Example for 100GBASE-R4 IP Core VariationThe TX transceiver PLLs are instantiated with two ATX PLL IP cores, one as the main ATX PLL and another as a clock buffer. The TX transceiver PLLs must always be instantiated outside the H-Tile Hard IP for Ethernet IP core.

To configure an ATX PLL as the main ATX PLL:

Select L-Tile/H-Tile Transceiver ATX PLL Stratix® 10 FPGA IP.
In the parameter editor, set the following parameter values:
- Set VCCR_GXB and VCCT_GXB supply voltage for the Transceiver to 1_1V.
- Set Primary PLL clock output buffer to GXT clock output buffer.
- Turn on Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx) or Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx).
- Turn on Enable GXT local clock output port (tx_serial_clk_gxt).
- Turn on Enable GXT clock buffer to above ATX PLL.
- Set GXT output clock source to Local ATX PLL.
- Set PLL output frequency to 12890.625 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 25.78125 Gbps data rate through the transceiver.
- Set PLL auto mode reference clock frequency to the value you specified for the PHY Reference Frequency parameter.

To configure an ATX PLL as a GXT transmit PLL with GXT clocks to adjacent GXT channels and GXT clock buffer ATX PLLs:

Set the ATX PLL operation mode drop-down as GXT mode.
Set the Enable GXT local clock output port (tx_serial_clk_gxt) .
Set the GXT output clock source drop-down as Local ATX PLL.
Select the Enable GXT output port to Input from ATX PLL above (gxt_input_from_abv_atx) or Input from ATX PLL below (gxt_input_from_blw_atx).
Tie off the pll_refclk0 pin to REFCLK pin, if the GXT clock buffer ATX PLL is not reconfigured to a GXT transmit PLL or GX transmit PLL.

Each PLL drives the tx_serial_clk input of two of the H-Tile Hard IP for Ethernet IP core PHY links. You must connect the PLLs to the H-Tile Hard IP for Ethernet IP core as follows:

Connect i_tx_pll_locked[0] and i_tx_pll_locked[1] from the H-Tile Hard IP for Ethernet IP core to the pll_locked signal of the main ATX PLL.

PLL	PLL Signal	H-Tile Hard IP for Ethernet
Main ATX PLL	`tx_serial_clk_gxt`	`i_tx_serial_clk[0]`
Main ATX PLL	`pll_locked`	`i_tx_pll_locked[0]` `i_tx_pll_locked[1]`
Clock Buffer	`tx_serial_clk_gxt`	`i_tx_serial_clk[1]`

Refer to the example compilation project or design example for working user logic that demonstrates one correct method to instantiate and connect the external PLLs.

When you generate an H-Tile Hard IP for Ethernet IP core, the software also generates the HDL code for an ATX PLL, in the simulation file <variation_name> /altera_xcvr_atx_pll_s10_htile_180/sim/ <variation_name> _altera_xcvr_atx_pll_s10_htile_180_ <random_string> .sv and the synthesis file <variation_name> /altera_xcvr_atx_pll_s10_htile_180/synth/ <variation_name> _altera_xcvr_atx_pll_s10_htile_180_ <random_string> .sv. However, the HDL code for the H-Tile Hard IP for Ethernet IP core does not instantiate the ATX PLL. If you choose to use the ATX PLL provided with the H-Tile Hard IP for Ethernet IP core, you must instantiate and connect the instances of the ATX PLL with the H-Tile Hard IP for Ethernet IP core in user logic.

If you generate your own ATX PLL, you must ensure its file name differs from the PLL provided with the IP core.

Note: If your design includes multiple instances of the H-Tile Hard IP for Ethernet IP core, do not use the ATX PLL HDL code provided with the IP core. Instead, generate new ATX PLL IP cores to connect in your design.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

2.4.3. Adding the Transceiver PLLs