6.12. Clocks

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 4/09/2024

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6.12. Clocks

You must set the transceiver reference clock (i_clk_ref) frequency to a value that the IP core supports. The H-Tile Hard IP for Ethernet IP core supports a clk_ref frequency of 644.53125 MHz ±100 ppm or 322.265625 MHz ±100 ppm. The ±100ppm value is required for any clock source providing the transceiver reference clock.

All H-Tile Hard IP for Ethernet IP core variations support the Synchronous Ethernet standard, whether or not you turn on the Enable SyncE parameter in the parameter editor. Sync-E variations provide the RX recovered clock as a top-level output signal.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the TX PLL reference clock with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the H-Tile Hard IP for Ethernet IP core performs the filtering.

Table 25. Clock InputsDescribes the input clocks that you must provide.
Signal Name	Description
`i_clk_tx`	The TX clock for the IP core is `i_clk_tx`. The frequency of this clock is 402.83203125 MHz.
`i_clk_rx`	The RX clock for the IP core is `i_clk_rx`. The frequency of this clock is 402.83203125 MHz.
`i_clk_ref`	The input clock `i_clk_ref` is the reference clock for the high-speed serial clocks and the datapath parallel clocks. This clock must have a frequency of 322.265625 MHz or 644.53125 MHz with a ±100 ppm accuracy per the IEEE 802.3-2015 Ethernet Standard. In addition, `i_clk_ref` must meet the jitter specification of the IEEE 802.3-2015 Ethernet Standard. The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the specific Device Datasheet for transceiver reference clock phase noise specifications.
`i_tx_serial_clk[1:0]`	High speed serial clocks driven by the ATX PLLs. IP core has two serial clocks, each driven from a separate ATX PLL. The frequency of these clocks is 12.890625 GHz. You must drive these clocks from ATX PLLs that you configure separately from the IP core. Refer to Adding the Transceiver PLLs.
`i_reconfig_clk`	Avalon® clock for the H-Tile Hard IP for Ethernet IP core transceiver reconfiguration interface and Ethernet reconfiguration interface. The clock frequency is 100-162 MHz. All transceiver reconfiguration interface and Ethernet reconfiguration interface signals are synchronous to `i_reconfig_clk`.

Table 26. Clock OutputsDescribes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of the IP core as well.
Signal Name	Description
`o_clk_pll_div64`	Hard IP for Ethernet block clock. The clock frequency is 402.83203125 MHz. This clock is reliable only after `i_tx_pll_locked` is asserted.
`o_clk_pll_div66`	Hard IP for Ethernet block clock × 64/66. The clock frequency is 390.625 MHz. This clock is reliable only after `i_tx_pll_locked` is asserted.
`o_clk_rec_div64`	Derived from RX recovered clock. This clock supports the Synchronous Ethernet standard. The RX recovered clock frequency is 402.83203125 MHz ±100 ppm during normal operation. This clock is reliable only after `o_cdr_lock` is asserted. The expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of `o_clk_rec_div64` or `o_clk_rec_div66`, to ensure the receive and transmit functions remain synchronized in your Synchronous Ethernet system. To do so you must include an additional component on your board. The IP core does not provide filtering.
`o_clk_rec_div66`	Derived from RX recovered clock. This clock supports the Synchronous Ethernet standard. The RX recovered clock frequency is 390.625 MHz ±100 ppm during normal operation. This clock is reliable only after `o_cdr_lock` is asserted. The expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of `o_clk_rec_div64` or `o_clk_rec_div66`, to ensure the receive and transmit functions remain synchronized in your Synchronous Ethernet system. To do so you must include an additional component on your board. The IP core does not provide filtering.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.12. Clocks