5. Reset

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 4/09/2024

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5. Reset

Ethernet registers control three distinct soft resets. These soft resets are not self-clearing. Software clears them by writing to the appropriate register. In addition, the IP core has three hard reset signals.

Asserting the external hard reset i_csr_rst_n or the soft reset eio_sys_rst returns all Ethernet registers to their original values, including the statistics counters. It also returns all transceiver registers to their original values. An additional dedicated reset signal, i_reconfig_reset, resets the transceiver reconfiguration and Ethernet reconfiguration interfaces.

Figure 18. Conceptual Overview of General IP Core Reset LogicThe three hard resets are top-level ports. The three soft resets are internal signals which are outputs of the PHY_CONFIG register. Software writes the appropriate bit of the PHY_CONFIG register to assert a soft reset.

The general reset signals reset the following functions:

soft_tx_rst, i_tx_rst_n: Resets the TX PCS and TX MAC. This reset leads to deassertion of the o_tx_lanes_stable output signal.
soft_rx_rst, i_rx_rst_n: Resets the RX PCS and RX MAC. This reset leads to deassertion of the o_rx_pcs_ready output signal.
eio_sys_rst, i_csr_rst_n: Resets the IP core. Resets the TX and RX MACs, Ethernet reconfiguration registers, PCS, and transceivers. This reset leads to deassertion of the o_tx_lanes_stable and o_rx_pcs_ready output signals. Use this signal to reset the IP core whenever the transceiver is recalibrated.

Table 13. Reset Signal Functions
Reset Signal	Block
Reset Signal	MAC TX Datapath	PCS TX Datapath	MAC RX Datapath	PCS RX Datapath	PHY	CSRs (MAC/PHY)	TX Statistics	RX Statistics
`i_csr_rst_n`, `eio_sys_rst`	√	√	√	√	√	√	√	√
`i_tx_rst_n`, `soft_tx_rst`	√	√	X	X	X	X	X	X
`i_rx_rst_n,` `soft_rx_rst`	X	X	√	√	X	X	X	X
`soft_clear_tx_stats`	X	X	X	X	X	X	√	X
`soft_clear_rx_stats`	X	X	X	X	X	X	X	√

In addition, the synchronous i_reconfig_reset signal resets the IP core transceiver reconfiguration interface and the Ethernet reconfiguration interface. Associated clock is the i_reconfig_clk, which clocks the two interfaces.

System Considerations

You should perform a system reset before beginning IP core operation by asserting and deasserting i_csr_rst_n and i_reconfig_reset signals together. To assert both signals, set i_csr_rst_n signal to 0 and i_reconfig_reset signal to 1. To deassert both signals, set i_csr_rst_n to 1 and i_reconfig_reset to 0. The IP core implements the correct reset sequence to reset the entire IP core.
If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.
If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit are corrupted.
If the ATX PLL loses lock, the IP core forces a transmit side and a receive side reset. To ensure the IP core also resets the Hard IP for Ethernet, you must assert the i_csr_rst_n signal after the ATX PLL loses lock.
If the IP core suffers loss of signal on the serial links, it asserts the receive reset.
While the eio_sys_rst reset is asserted, do not access any other registers.
If the auto-negotiation and link training (AN/LT) are enabled, do not use eio_sys_rst reset until AN/LT operation is complete. In the data mode, you can use eio_sys_rst reset as long as no other Avalon-MM access is in progress.

The following diagrams show the reset sequences for TX and RX datapaths when you assert i_tx_rst_n and i_rx_rst_n reset signals.

Figure 19. TX Datapath Reset Sequence

Figure 20. RX Datapath Reset Sequence

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

5. Reset

System Considerations