Supply Pins
Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| VCCP | Power | VCCP supplies power to the periphery. | VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. Connect VCCP pins to a 0.9V supply. For more information about the performance and power consumption, refer to the Intel® Quartus® Prime software timing reports and Intel® Cyclone® 10 GX Early Power Estimator (EPE). For details about the recommended operating conditions, refer to the Electrical Characteristics in the device datasheet. Use the Intel® Cyclone® 10 GX Early Power Estimator (EPE) to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. See Notes 2, 3, 4, 5, 6, and 10. |
| VCC | Power | VCC supplies power to the core. VCC also supplies power to the Hard IP for PCI Express cores. | VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. Connect VCC pins to a 0.9V supply. For more information about the performance and power consumption, refer to the Intel® Quartus® Prime software timing reports and Intel® Cyclone® 10 GX Early Power Estimator (EPE). For details about the recommended operating conditions, refer to the Electrical Characteristics in the device datasheet. Use the Intel® Cyclone® 10 GX Early Power Estimator (EPE) to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. See Notes 2, 3, 4, 5, 6, and 10. |
| VCCPT | Power | Power supply for the programmable power technology and I/O pre-drivers. | Connect VCCPT to a 1.8V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:
Provide a minimum decoupling of 1uF for the VCCPT power rail near the VCCPT pin. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices. See Notes 2, 3, 4, 7, and 10. |
| VCCA_PLL | Power | PLL analog power. | Connect VCCA_PLL to a 1.8V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT. See Notes 2, 3, 4, 7, and 10. |
| VCCIO([2][A,J,K,L], [3][A,B]) | Power | These are I/O supply voltage pins for banks 1 through 12. Each bank can support a different voltage level. Supports VCCIO standards that include Diff HSTL/HSTL(12, 15, 18), Diff SSTL/SSTL(12, 125, 135, 15, 18), Diff HSUL/HSUL(12), Diff POD 12, LVDS/Mini_LVDS/RSDS, 1.2V, 1.5V, 1.8V, 2.5V, 3.0V I/O standards. | Connect these pins to 1.2V, 1.25V, 1.35V, 1.5V, 1.8V, 2.5V, or 3.0V supplies, depending on the I/O standard required by the specified bank. When these pins require the same voltage level as VCCPGM, you have the option to tie them to the same regulator as VCCPGM. Not all I/O banks support 2.5V or 3.0V supplies. For more details, refer to the I/O and High Speed I/O in Intel® Cyclone® 10 GX Devices. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices. See Notes 2, 3, 4, 8, and 10. |
| VCCPGM | Power | Configuration pins power supply. | Connect these pins to a 1.2V, 1.5V, or 1.8V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank to the same regulator as VCCPGM, ranging from 1.2V, 1.5V, or 1.8V. When you do not use dual-purpose configuration pins for configuration, connect VCCIO to 1.2V, 1.25V, 1.35V, 1.5V, or 1.8V. When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO. Provide a minimum decoupling of 47nF for the VCCPGM power rail near the VCCPGM pin. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices. See Notes 2, 3, 4, and 10. |
| VCCERAM | Power | Memory power pins. | Connect all VCCERAM pins to a 0.9V linear or low noise switching power supply. VCC, VCCP, and VCCERAM must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. See Notes 2, 3, 7, and 10. |
| VCCBAT | Power | Battery back-up power supply for design security volatile key register. | When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2V – 1.8V. When not using the volatile key, tie this pin to a supply ranging from 1.5V to 1.8V. If 1.8V is selected when the design security key is unused, you have the option to source this pin from the same regulator as VCCPT. This pin must be properly powered as per the recommended voltage range as the POR circuitry of the Intel® Cyclone® 10 GX devices monitoring VCCBAT. Provide a minimum decoupling of 47nF for the VCCBAT power rail near the VCCBAT pin. For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices. |
| GND | Ground | Device ground pins. | All GND pins should be connected to the board ground plane. |
| VREFB[[2][A,J,K,L], [3][A,B]]N0 | Power | Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then use these pins as voltage-reference pins for the bank. | If VREF pins are not used, connect them to either the VCCIO in the bank in which the pin resides or GND. See Notes 2, 8, 10, and 11. |
| VCCLSENSE | Power | Differential sense line to external regulator. | VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source. Connect VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs when ICC current >30A. VCCLSENSE and GNDSENSE line connections are optional if ICC current <=30A. However, Intel® recommends connecting the VCCLSENSE and GNDSENSE for regulators that support remote sense line feature. If you do not use the VCCLSENSE and GNDSENSE pins, leave the VCCLSENSE and GNDSENSE pins unconnected. |
| GNDSENSE | Ground | ||
| ADCGND | Ground | Dedicated quiet ground. | If you are using voltage sensor, you must connect ADCGND plane to board GND through a proper isolation filter with ferrite bead. Select the ferrite bead according to the frequency of the noise profile when it shows the maximum noise level. Alternatively, you can choose the ferrite bead based on the ADCGND maximum current value as well, which is 10 mA. If you are not using voltage sensor, isolation filter with ferrite bead to board GND is optional. |