Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

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ID 683417
Date 10/29/2021
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Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines x
Intel® Cyclone® 10 GX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices Document Revision History for the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Reference Pins Supply Pins Transceiver Pins Notes to Intel® Cyclone® 10 GX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices x
Example 1— Intel® Cyclone® 10 GX Example 2— Intel® Cyclone® 10 GX
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

Differential I/O Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 5.  Differential I/O Pins
Pin Name Pin Functions Pin Description Connection Guidelines
LVDS[2,3][A,B,J,K,L]_[1:24]p , LVDS[2,3][A,B,J,K,L]_[1:24]n I/O, TX/RX channel These are true LVDS receiver/transmitter channels on column I/O banks. Each I/O pair can be configured as LVDS receiver or LVDS transmitter. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Connect unused pins as defined in the Intel® Quartus® Prime software.
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