Clock and PLL Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
CLK_[2,3][A,B,J,K,L]_[0,1]p | I/O, Clock Input | Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT RD, single-ended input OCT RT, and single-ended output OCT RS are supported on these pins. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. |
CLK_[2,3][A,B,J,K,L]_[0,1]n | I/O, Clock Input | Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT RD, single-ended input OCT RT, and single-ended output OCT RS are supported on these pins. |
Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. |
PLL_[2,3][A,B,J,K,L]_FB[0,1] | I/O, Clock | Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pin. For more information about the supported pins, refer to the device pinout file. | Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. |
PLL_[2,3][A,B,J,K,L]_CLKOUT[0:1] , PLL_[2,3][A,B,J,K,L]_CLKOUT[0:1]p | I/O, Clock | I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pinout file. | Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. |
PLL_[2,3][A,B,J,K,L]_CLKOUT[0:1]n | I/O, Clock | I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pinout file. | Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Intel® Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. |