2021.10.29 |
Added Table: 3V Compatible I/O Pins. |
2020.12.23 |
Removed the sentence "For better performance, isolate VCCR_GXB and VCCT_GXB from each other with at least 30 dB of isolation for a 1 MHz to 100 MHz bandwidth." from Table: Power Supply Sharing Guidelines for Intel Cyclone 10 GX with Transceiver Data Rate <= 12.5 Gbps for Chip-to-Chip Applications (Transceiver Data Rate <= 6.6 Gbps for Backplane Applications).
Note: If you have implemented this recommendation on your board and your design functions properly, you do not need to rework the board.
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2019.07.01 |
- Updated the connection guidelines of the TMS and TDI pins to provide more clarity.
- Updated the connection guidelines of the INIT_DONE pin to provide more clarity.
- Updated the connection guidelines of the VCCBAT pin to provide more clarity.
- Updated the connection guidelines of the nPERSTL0 pin.
- Updated the connection guidelines of the VCCP and VCC pins.
- Updated the connection guidelines of the VCCR_GXB[L1] [C,D] and VCCT_GXB[L1] [C,D] pins.
- Updated the connection guidelines of the GXB[L1][C,D]_RX_[0:5]p, GXB[L][1][C,D]_REFCLK_CH[0:5]p, GXB[L1][C,D]_RX_[0:5]n, and GXB[L][1][C,D]_REFCLK_CH[0:5]n pins.
- Updated the requirement for VCCT_GXBL pin in the Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications section.
- Updated the Example Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX with Transceiver Data Rate <= 11.3 Gbps for Chip-to-Chip Applications and Example Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX with Transceiver Data Rate <= 12.5 Gbps for Chip-to-Chip Applications (Transceiver Data Rate <= 6.6 Gbps for Backplane Applications) figures to include grouping legend for the power rails.
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