Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

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ID 683417
Date 10/29/2021
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines x
Intel® Cyclone® 10 GX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices Document Revision History for the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Reference Pins Supply Pins Transceiver Pins Notes to Intel® Cyclone® 10 GX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices x
Example 1— Intel® Cyclone® 10 GX Example 2— Intel® Cyclone® 10 GX
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

Notes to Intel® Cyclone® 10 GX Pin Connection Guidelines

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Intel® provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. These pin connection guidelines are created based on the Intel® Cyclone® 10 GX device variant.
  2. Select the capacitance values for the power supply after you consider the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. Calculate the target impedance for the power plane based on current draw and voltage drop requirements of the device/supply. Then, decouple the power plane using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Consider proper board design techniques such as interplane capacitance with low inductance for higher frequency decoupling. Refer to the PDN tool.
  3. Use the Intel® Cyclone® 10 GX Early Power Estimator (EPE) to determine the current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  4. These supplies may share power planes across multiple Intel® Cyclone® 10 GX devices.
  5. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
  6. Example 1 and Example 2 illustrate the power supply sharing guidelines for the Intel® Cyclone® 10 GX devices.
  7. Low Noise Switching Regulator—defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast transient response. The switching frequency range is not an Intel® requirement. However, Intel® does require the Line Regulation and Load Regulation meet the following specifications:
    • Line Regulation < 0.4%
    • Load Regulation < 1.2%
  8. The number of modular I/O banks on Intel® Cyclone® 10 GX devices depends on the device density. For the indexes available for a specific device, please refer to the I/O Bank section in the Intel Cyclone 10 GX Device Handbook.
  9. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel subject to the protocol or design requirement. PCI Express protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  10. Decoupling for these pins depends on the design decoupling requirements of the specific board.
  11. Do not connect voltage above 1.8V to the VREFB[[2][A,J,K, L], [3][A,B]]N0 pins. For 3V I/O banks, tie unused VREF pins to GND.
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