Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.6. Test Result Comments

In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRSB checker. For test case with LMF = 211, the data rate is reduced to 2457 Mbps to limit the ADC sample clock to less than 250 MHz. The following table describes the scenarios where there is a difference in the data rate.

Table 11.   Sample Rate Implication for Test Case with LMF = 211
Item Scenario 1 Scenario 2 Remark
Data rate 4915 Mbps 2457 Mbps Data rate is within the operating condition of AD9250.
Link clock = data rate/40 122.88 MHz 61.44 MHz Link clock frequency is determined by the data rate.
ADC sample clock must be ≤ ADC maximum sampling rate 491.52 MHz 245.76 MHz Sample clock frequency in scenario 1 is beyond the operating condition of AD9250.

The link clock count variation in the deterministic latency measurement is caused by the word alignment, where control characters fall into the next cycle of data some time after realignment. This makes the duration of the ILAS phase longer by one link clock some time after reset.

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