Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.3.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute.

Figure shows the conceptual test setup for data integrity checking.

Figure 4. Data Integrity Check Using PRBS Checker


The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.

Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping. The following signals in altera_jesd204_transport_rx_top.v are tapped:
  • jesd204_rx_data_valid
  • jesd204_rx_link_data_valid
  • jesd204_rx_link_error
The following signals in jesd204b_ed.v are tapped:
  • data_error[M-1:0]
  • jesd204_rx_int

M is the number of converters.

The rxframe_clk is used as the SignalTap II sampling clock.

The data_error signal is the PRBS checker's pass or fail indicator.

  • The jesd204_rx_data_valid and jesd204_rx_link_data_valid signals is asserted.
  • The jesd204_rx_link_error and jesd204_rx_int signals is deasserted.
Level Two Title