Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.2. Hardware Setup

Set up the development kit with the ADI AD9250 daughter card module installed to the board's FMC connector.
Figure 1. Hardware Setup for Arria V GT Development Kit
  • The AD9250 module derives power from the FMC connector on the development board.
  • The AD9250 module supplies the device clock to FPGA 2.
  • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module.


Figure 2. Hardware Setup for Arria V SoC Development Kit
  • The AD9250 module derives power from the FMC connector on the development board.
  • The AD9250 module supplies clock to the FPGA and ADC.
  • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9250 module.


Figure 3. System Diagram

The system-level diagram shows how the different modules connect in this design.

In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices.



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