1.3.4. Deterministic Latency (Subclass 1)
Figure shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9250 and JESD204B IP core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 5. Deterministic Latency Test Setup Block Diagram
The deterministic latency measurement block checks the deterministic latency by measuring the number of link clock counts between the start of deassertion of SYNC~ to the first user data output.
Figure 6. Deterministic Latency Measurement Timing Diagram
With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B IP core performs a single SYSREF detection. The SYSREF N-shot mode is enabled on the AD9250 for this deterministic measurement.
| Test Case | Objective | Description | Passing Criteria |
|---|---|---|---|
| DL.1 | Check the LMFC alignment. | Check that the FPGA and ADC are aligned to the desired LMF periods. SYSREF detection is always enabled. Observe the sysref_lmfc_err signal from the Signal Tap II Logic Analyzer. |
The sysref_lmfc_err signal should not be triggered. |
| DL.2 | Check the SYSREF capture. | Check that the FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both the FPGA and ADC are also repetitively reset. Observe the csr_rbd_count signal from the Signal Tap II Logic Analyzer. |
If the SYSREF is captured correctly and the LMF counter restarts, the csr_rbd_count value should only drift a little for every reset due to word alignment. |
| DL.3 | Check the latency from start of deassertion of SYNC~ to the first user data output. | Check that the latency is fixed for every FPGA reset. Repetitively reset the FPGA upon assertion of RX valid. Record the number of link clocks count from start of deassertion of SYNC~ to the first user data output. Continuously compare the current test (n) that records the number of link clocks from deassertion of SYNC~ to the first user data output with the previous test (n-1) record. |
Consistent latency from the start of deassertion of SYNC~ to the first user data output latency. |