Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.3.3. Descrambling

The PRBS checker at the RX transport layer checks the data integrity of descrambler.

The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.

Table 4.  Descrambler Test Cases
Test Case Objective Description Passing Criteria
SCR.1 Check the functionality of the descrambler.

Enable scrambler at the ADC and descrambler at the RX JESD204B IP core.

The signals that are tapped in this test case are similar to test case TL.1

  • The jesd204_rx_data_valid and jesd204_rx_link_data_valid signals is asserted.
  • The jesd204_rx_link_error and jesd204_rx_int signals is deasserted.
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