L/H-Tile Hard IP for PCI Express* IP Core Release Notes

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ID 683412
Date 10/27/2023
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1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-Tile Hard IP for PCI Express* IP Cores for 23.2 1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1 1.3. L/H-Tile Hard IP for PCI Express* IP Cores for 21.4 1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4 1.6. L/H-Tile Hard IP for PCI Express* IP Core v19.3 1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1 1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1 1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0 1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1
1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 x
1.4.1. L/H-Tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.4.2. L/H-Tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes

1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 6.  v21.0.0 2020.12.14
Intel® Quartus® Prime Version Description Impact
20.4 Migrating a design using an L/H-Tile Avalon® Streaming, Avalon® Memory-mapped or Avalon® Memory-mapped+ IP from an earlier Intel® Quartus® Prime version to the 20.4 version requires an IP upgrade. You must regenerate any design using an L/H-Tile Avalon® Streaming, Avalon® Memory-mapped or Avalon® Memory-mapped+ IP when moving from an earlier Intel® Quartus® Prime version to the 20.4 version.
The names of the L/H-Tile IPs for PCI Express have been changed to meet new legal guidelines. The abbreviations " Avalon® -ST" and " Avalon® -MM" in the names of the L/H-Tile IPs for PCI Express have been replaced with " Avalon® Streaming" and " Avalon® Memory-mapped", respectively.
The parameters to enable the Multi-function and Function-Level Reset (FLR) features have been removed from the IP Parameter Editor of the L/H-Tile Avalon® Memory-mapped+ IP. Multi-function and FLR support are not available in this Intel® Quartus® Prime release for the L/H-Tile Avalon® Memory-mapped+ IP.
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