1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1
Description | Impact |
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Added the Link Inspector Avalon-MM Interface to the Avalon® -ST, Avalon® -MM and Avalon® -MM Hard IP+ for PCI Express* IPs. | This interface allows you to access low-level link status information from the PCIe Hard IP, XCVR or PLL blocks via the Link Inspector without using the System Console. |
Added the completion timeout checking feature to the Avalon® -MM Hard IP+ for PCI Express* IP. | This new option in the GUI (under the Avalon® -MM Settings tab) allows you to receive a completion timeout error indicator on either the rddm_tx_data_o[15] port (if the Read Data Mover issued a Read operation to the host) or the bas_response_o[1:0] ports (if the Bursting Avalon® Slave forwarded a Read operation to the host). |
Added the feature to trigger MSI interrupts via the rxm_irq_i ports to the Avalon® -MM for PCI Express* IP. | This feature allows the IP core to convert a rising edge on one of the rxm_irq_i ports to an MSI interrupt and send it to the Root Port.
Note: the rxm_irq_i ports are not available when the IP core is operating in DMA mode.
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