L/H-Tile Hard IP for PCI Express* IP Core Release Notes

Download PDF
ID 683412
Date 10/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-Tile Hard IP for PCI Express* IP Cores for 23.2 1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1 1.3. L/H-Tile Hard IP for PCI Express* IP Cores for 21.4 1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4 1.6. L/H-Tile Hard IP for PCI Express* IP Core v19.3 1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1 1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1 1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0 1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1
1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 x
1.4.1. L/H-Tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.4.2. L/H-Tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes

1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1

Table 11.  17.1 November 2017
Description Impact
Initial release. N/A
VHDL compilation and simulation are not supported in the current release. You can only simulate in Verilog in the current release.

The automatically generated simple DMA design example has timing issues.

This timing problem does not affect DMA designs that use the internal descriptor controller or DMA designs that use an external DMA controller to drive the internal Read and Write Data Movers. These designs close timing and function correctly in hardware.

You can simulate the simple DMA design and successfully and generate an SRAM Object file (*.sof). However, if you download the *.sof to hardware, the hardware will fail.

Single Root I/O Virtualization (SR-IOV) support for H-Tile variants is preliminary in the 17.1 release.

You can enable SR-IOV using the parameter editor. SR-IOV supports basic simulation and compilation. However, SR-IOV is not fully verified. You may find functional problems in the current release.
The Root Port is preliminary in the 17.1 release. You can enable the Root Port using the parameter editor. The Root Port supports basic simulation and compilation. However, the Root Port is not fully verified. You may find functional problems in the current release.
The Avalon® Memory-Mapped ( Avalon® -MM) DMA functionality is preliminary in the 17.1 release. You can use the Avalon® -MM DMA functionality in the current release. Avalon® -MM supports simulation and compilation. However, this functionality has not been fully verified. You may find functional problems.
Upon reboot, the Intel® Stratix® 10 Hard IP for PCI Express* IP Core might be unable to exit BIOS enumeration. This problem affects L-Tile ES1 and ES2 and H-Tile ES1 devices. It will be fixed in a future release.

The link acknowledge logic in the Intel® Stratix® 10 H-Tile ES2 devices has a encoding error. This encoding error results in the following incorrect link widths:

Actual Link Width Link Acknowledge
x1 x16
x2 x1
x4 x2
x8 x4
x16 x8
This problem will be fixed in a future release.
Related Information
Level Two Title