L/H-Tile Hard IP for PCI Express* IP Core Release Notes

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ID 683412
Date 10/27/2023
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Document Table of Contents x
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-Tile Hard IP for PCI Express* IP Cores for 23.2 1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1 1.3. L/H-Tile Hard IP for PCI Express* IP Cores for 21.4 1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4 1.6. L/H-Tile Hard IP for PCI Express* IP Core v19.3 1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1 1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1 1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0 1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1
1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 x
1.4.1. L/H-Tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.4.2. L/H-Tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes

1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

Table 2.  v22.2.1 2023.04.03
Intel® Quartus® Prime Version Description Impact
23.1 Changed the IP name from Intel® L-/H-Tile Avalon® memory mapped IP for PCI Express* to L-/H-Tile Avalon® Memory-Mapped Intel® FPGA IP for PCI Express* . The IP name was changed in the IP Parameter Editor of Intel® Quartus® Prime as well as in the User Guides. There is no impact to the design of the IP.
Platform Designer now gives an explicit warning when the input BAR size exceeds the limit defined by the BAR address width. The warning is given for informational purpose only. It does not prevent the IP generation.
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