1.3.2. Receiver Transport Layer
To check the data integrity of the payload data stream through the RX JESD204B IP Core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core. The PRBS checker in the FPGA fabric checks data integrity for one minute.
This figure shows the conceptual test setup for data integrity checking.
The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
TL.1 |
Check the transport layer mapping using PRBS-9 test pattern. |
The following signal in altera_jesd204_transport_rx_top.sv is tapped:
The following signals in jesd204b_ed.sv are tapped:
The rxframe_clk signal is used as the SignalTap II sampling clock. The data_error signal indicates a pass or fail for the PRBS checker. |
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