AN 753: Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

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ID 683405
Date 11/02/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. AN 753 Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD6676 Hardware Checkout Report

1.4. JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M and F) in this hardware checkout are natively supported by the AD6676. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD6676 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 6.  JESD204B IP Core Parameter Configuration

Configuration

Setting

Setting

LMF

222

124

HD

0

0

S

1

1

N

16

16

N’

16

16

CS

0

0

CF

0

0

ADC Sampling Clock (GHz)

2.94912

2.94912

FPGA Device Clock (MHz) 3

245.76

122.88

FPGA Management Clock (MHz)

100

100

FPGA Frame Clock (MHz)

122.88

122.88

FPGA Link Clock (MHz) 4

122.88

122.88

Lane Rate (Gbps)

4.9152

4.9152

Character Replacement

Enabled

Enabled

Data Pattern 5

  • PRBS-9
  • Ramp
  • PRBS-9
  • Ramp
3 The device clock is used to clock the transceiver.
4 The frame clock and link clock is derived from the device clock using an internal PLL.
5 The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3 only.
Level Two Title