CGS.1

Check whether sync request is deasserted after correct reception of four successive /K/ characters.

The following signals in <ip_variant_name> _inst_phy.v are tapped:

• jesd204_rx_pcs_data[(L*32)-1:0]
• jesd204_rx_pcs_data_valid[L-1:0]
• jesd204_rx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name> .v are tapped:

• rx_dev_sync_n
• jesd204_rx_int

The rxlink_clk signal is used as the SignalTap II sampling clock.

Each lane is represented by a 32-bit data bus in the jesd204_rx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

• /K/ character or K28.5 (0xBC) is observed at each octet of the jesd204_rx_pcs_data bus.
• The jesd204_rx_pcs_data_valid signal is asserted to indicate data from the PCS is valid.
• The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are observed.
• The rx_dev_sync_n signal is deasserted after correct reception of at least four successive /K/ characters.
• The jesd204_rx_int signal is deasserted if there is no error.

CGS.2

Check full CGS at the receiver after correct reception of another four 8B/10B characters.

The following signals in <ip_variant_name> _inst_phy.v are tapped:

• jesd204_rx_pcs_errdetect[(L*4)-1:0]
• jesd204_rx_pcs_disperr[(L*4)-1:0] ¹

The following signal in <ip_variant_name> .v is tapped:

• jesd204_rx_int

The rxlink_clk signal is used as the SignalTap II sampling clock.

The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr, and jesd204_rx_int signals should not be asserted during CGS phase.