1.3.1.2. Initial Frame and Lane Synchronization
Test Case |
Objective |
Description |
Passing Criteria |
---|---|---|---|
ILA.1 |
Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters. |
The following signals in <ip_variant_name> _inst_phy.v are tapped:
The following signals in <ip_variant_name> .v are tapped:
The rxlink_clk signal is used as the SignalTap II sampling clock. Each lane is represented by a 32-bit data bus in the jesd204_rx_pcs_data signal. The 32-bit data bus is divided into 4 octets. |
|
ILA.2 |
Check the JESD204B configuration parameters from the ADC in the second multiframe. |
The following signals in <ip_variant_name> _inst_phy.v are tapped:
The following signal in <ip_variant_name> .v is tapped:
The rxlink_clk signal is used as the SignalTap II sampling clock. The system console access the following registers:
The content of 14 configuration octets in the second multiframe is stored in these 32-bit registers— ilas_octet0, ilas_octet1, ilas_octet2, and ilas_octet3. |
|
ILA.3 |
Check the lane alignment |
The following signals in <ip_variant_name> _inst_phy.v are tapped:
The following signals in <ip_variant_name> .v are tapped:
The rxlink_clk signal is used as the SignalTap II sampling clock. |
|