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3. Power Management Controller Reference Design
This reference design utilizes the low-power feature supported in Intel® MAX® 10 devices. The following figure shows the related block diagrams in the power management controller reference design.
Port Name | Input/Output | Description |
---|---|---|
sleep | Input | Sleep control. |
rst_n | Input | Active low reset signal. |
clk | Input | Clock signal. |
sleep_status | Output | Sleep status of the system. This signal is asserted high when the system is entering the sleep mode condition. This signal is de-asserted when the system exits the sleep mode condition completely. |
gpio_pad_output[3:0] | Output | General-purpose I/O (GPIO) output ports. |
cnt_value[7:0] | Output | Free-running counter value in user logic. |
cnt_enter_sleep[7:0] | Output | Counter value when the system is entering sleep mode condition. |
cnt_exit_sleep[7:0] | Output | Counter value when the system is exiting sleep mode condition. |
The power management controller design is a FSM showing the state of powering down and powering up global clocks (GCLKs) and I/O buffers. The internal oscillator, clock control block, and I/O buffer are intellectual property (IP) that are supported by the Intel® Quartus® Prime software and you can instantiate the IPs from the IP catalog. The user logic can be any logical circuitry that are implemented using logic element (LE) and an embedded component such as DSP and internal memory in your design. In this reference design, the user logic used is a free-running 8-bit counter. The cnt_enter_sleep and cnt_exit_sleep ports are used to ensure user logic can enter and exit sleep mode without data corruption. It is expected for that cnt_enter_sleep[7:0] and cnt_exit_sleep[7:0] are at the same value after the user logic enter and exit sleep mode. gpio_pad_output ports demonstrate tri-stated state of the GPIO when the system is in sleep mode.