Intel® MAX® 10 Power Management User Guide

ID 683400
Date 5/27/2022
Public
Document Table of Contents

3.1. Clock Control Block

The ALTCLKCTRL Intel® FPGA IP core (clk_control_altclkctrl) is an IP provided in the Intel® Quartus® Prime software. This IP is used to control the clock system in the device. The GCLKs that drive through the device can be dynamically powered down by controlling the active high ena signal. The ena port is an input to the clock control IP block. When this IP is instantiated, select the ena port to enable the controls of GCLKs.