Intel® MAX® 10 Power Management User Guide

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ID 683400
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Power Management Overview 2. Intel® MAX® 10 Power Management Features and Architecture 3. Power Management Controller Reference Design 4. Intel® MAX® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® MAX® 10 Power Management User Guide
2. Intel® MAX® 10 Power Management Features and Architecture x
2.1. Power Supply Device Options 2.2. Power-On Reset Circuitry 2.3. Power Management Controller Scheme 2.4. Hot Socketing
2.1. Power Supply Device Options x
2.1.1. Single-Supply Device 2.1.2. Dual-Supply Device 2.1.3. Comparison of the Intel® MAX® 10 Power Supply Device Options 2.1.4. Power Supply Design
2.1.4. Power Supply Design x
2.1.4.1. Transient Current
2.2. Power-On Reset Circuitry x
2.2.1. Power Supplies Monitored and Not Monitored by the POR Circuitry 2.2.2. Instant-On Support
2.3. Power Management Controller Scheme x
2.3.1. Power Management Controller Architecture
2.3.1. Power Management Controller Architecture x
2.3.1.1. Internal Oscillator 2.3.1.2. I/O Buffer Power Down 2.3.1.3. Global Clock Gating
2.4. Hot Socketing x
2.4.1. Hot-Socketing Specifications 2.4.2. Hot-Socketing Feature Implementation
2.4.1. Hot-Socketing Specifications x
2.4.1.1. Drive Intel® MAX® 10 Devices Before Power Up 2.4.1.2. I/O Pins Remain Tri-stated During Power up
3. Power Management Controller Reference Design x
3.1. Clock Control Block 3.2. I/O Buffer 3.3. Internal Oscillator 3.4. Power Management Controller 3.5. Entering or Exiting Sleep Mode 3.6. Hardware Implementation and Current Measurement
3.4. Power Management Controller x
3.4.1. Entering State 3.4.2. Sleep State 3.4.3. Exiting State 3.4.4. Awake State
3.5. Entering or Exiting Sleep Mode x
3.5.1. Entering Sleep Mode 3.5.2. Exiting Sleep Mode 3.5.3. Timing Parameters
1. Intel® MAX® 10 Power Management Overview
2. Intel® MAX® 10 Power Management Features and Architecture
3. Power Management Controller Reference Design
4. Intel® MAX® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® MAX® 10 Power Management User Guide

3.6. Hardware Implementation and Current Measurement

This design is implemented using the 10M50DAF484C6 device. You can implement this design using any Intel® MAX® 10 device. This design runs on the Intel® MAX® 10 Development Kit Board to show current and power relative between user mode and sleep mode.

The resource utilization of this design is as follows:

  • 42,000 LEs (84% of total LEs)—gray counter top module utilizes most of the LEs in the device
  • 33 I/O pins (9% of total pins)—covering 3 input pins and 30 output pins

The current in this design is measured using a current monitor component (the Linear Technologies LTC 2990). The measured current is further processed by a pre-programmed design in a MAX II device. The measured current is shown on Intel FPGA power monitor GUI when the PowerMonitor.exe is launched. You will see a current monitor for each of the main supplies to the Intel® MAX® 10 device as follows:

  • 2.5V_CORE5
  • 2.5V_VCCIO
  • 1.5V_VCCIO
  • 1.2V_VCC

For design demonstration purpose, the push button is used for sleep control and the LEDs are used for sleep status. Thus, these signals have been inverted on the pin level. To enter sleep mode, press and hold the push button USER_PB0. To release the design to user mode, release the push button USER_PB0. LED0 indicates the sleep status of the device. LED0 is turned on when the device enters sleep mode and is turned off when the device is in user mode. During sleep mode, gpio_pad_output ports connecting to LED1–LED4 are tri-stated and then turned off.

Figure 12. Current Monitor for Each Supply

In sleep mode, all GCLK networks are gated and all output buffers are disabled.

Table 8.  Comparison of Current and Power Consumption
Current and Power User Mode Sleep Mode
1.2V_ICC (mA) 160 11
2.5V_ICCA (mA) 28 28
1.5V_ICCIO (mA) 1.3 1.0
2.5V_ICCIO (mA) 2.7 1.2
Total power (mW) 270 88

The results show an approximate 93% reduction in the core current (1.2V_ICC) consumption and an approximate 56% reduction in I/O current (2.5V_ICCIO) consumption in sleep mode relative to user mode. The total power consumption reduction in this design in sleep mode is about 68%.

5 This is 2.5V_VCCA.
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