Intel® MAX® 10 Power Management User Guide

ID 683400
Date 5/27/2022
Public
Document Table of Contents

3.2. I/O Buffer

The GPIO Lite Intel® FPGA IP core (altera_gpio_lite) is implemented as an input, output, or bidirectional I/O buffer. You can control the power down of these I/O buffers by enabling the nsleep port of the input buffer and the oe port of the output buffer. The oe and nsleep ports are pulled low by the power management controller design to power down the I/O buffers during sleep mode. Intel recommends using a separate GPIO Lite Intel® FPGA IP core when some of the I/O buffer is not required to be powered down.