Visible to Intel only — GUID: umh1655416239002
Ixiasoft
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set
3.2. 845719: A Load May Read Incorrect Data
3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK
3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail
3.5. 711668: Configuration Extension Register Has Wrong Value Status
3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow
3.7. 855873: An Eviction Might Overtake a Cache Clean Operation
3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output
3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing
3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception
3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results
3.12. 851672: ETM May Trace an Incorrect Exception Address
3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode
3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment
3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address
3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events
3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN
3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
Visible to Intel only — GUID: umh1655416239002
Ixiasoft
2.3.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
Description:
In the Arm* AMBA* AXI* and ACE* Protocol Specification ( Arm* IHI 0022H.c), the following is described:
A3.3 Relationships between the channels
The AXI* protocol requires the following relationships to be maintained:
- A write response must always follow the last write transfer in a write transaction.
- Read data must always follow the read address of the data.
- Channel handshakes must conform to the dependencies defined in Dependencies between channel handshake signals.
The protocol does not define any other relationship between the channels. The lack of relationship means, for example, that the write data can appear at an interface before the write address for the transaction. This can occur if the write address channel contains more register stages than the write data channel. Similarly, the write data may appear in the same cycle as the address.
There are times when the Intel® Stratix® 10 device must perform a “fence and drain” operation on the FPGA-to-SDRAM bridge, which means that it blocks all future transactions and completes all current transactions across the AXI bridges. During this operation, the system does not account for the above AXI protocol specification, where the write data can appear at the interface before the write address for the transaction. This can cause corrupt/invalid data to be left in the system, which can cause undefined behavior or system halt.
Workaround:
The solution is to require the AXI initiator (the user logic in the fabric portion of the device) to align the AXI write data channel and the AXI write address channel at the FPGA-to-SDRAM bridge, or where it enters the Platform Designer generated interconnect. You must ensure WVALID is not asserted before AxVALID is asserted.
Status:
Affects:
- Intel® Stratix® 10 SX 400
- Intel® Stratix® 10 SX 650
- Intel® Stratix® 10 SX 850
- Intel® Stratix® 10 SX 1100
- Intel® Stratix® 10 SX 1650
- Intel® Stratix® 10 SX 2100
- Intel® Stratix® 10 SX 2500
- Intel® Stratix® 10 SX 2800
Status: No planned fix