Intel® Stratix® 10 SX Device Errata

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ID 683399
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Document Revision History for Intel® Stratix® 10 SX Device Errata
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices x
2.1. FPGA 2.2. Device Power Supply, Core, Configuration and I/O 2.3. Hard Processor System
2.2. Device Power Supply, Core, Configuration and I/O x
2.2.1. M20K Simple Quad-Port Mode Support
2.3. Hard Processor System x
2.3.1. HPS Stops on the First Read Request to SDRAM 2.3.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Document Revision History for Intel® Stratix® 10 SX Device Errata

3.7. 855873: An Eviction Might Overtake a Cache Clean Operation

Description

The Cortex*-A53 MPCore* processor supports instructions for cache clean operations. To avoid data corruption, the processor must ensure correct ordering between evictions and cache clean operations for the same address.

Because of this erratum, the processor can issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. The processor can also issue transactions that become outstanding in the interconnect at the same time. This situation violates the AXI Coherency Extensions (ACE) protocol specification.

This erratum occurs when the following conditions are met:
  1. One or both of the following are true:
    • L2ACTLR[14] is set to 1. This setting allows WriteEvict transactions on the ACE interface when the processor evicts data that it holds in the UniqueClean state.
    • L2ACTLR[3] is set to 0. This setting allows Evict transactions on the ACE interface when the processor evicts clean data.
  2. A CPU executes a cache clean-by-address operation for a line that is present and dirty in the L2 cache.
  3. A CPU performs any type of memory access to the same set. Memory access types can include a pagewalk, instruction fetch, cache maintenance operation or data access.
  4. An instruction fetch to the same set triggers an L2 cache eviction.
  5. A present and dirty cache line that is selected for L2 cache eviction at the same time it is targeted for a cache clean operation.

Impact

Because of this erratum transactions are erroneously reordered in the interconnect, resulting in data corruption.

Workaround

You can workaround this erratum by changing the cache clean-by-address operations to cache clean-and-invalidate operations. To enable these operations, set CPUACTLR.ENDCCASCI to 1.

Category

Category 2
Level Two Title