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3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set
3.2. 845719: A Load May Read Incorrect Data
3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK
3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail
3.5. 711668: Configuration Extension Register Has Wrong Value Status
3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow
3.7. 855873: An Eviction Might Overtake a Cache Clean Operation
3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output
3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing
3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception
3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results
3.12. 851672: ETM May Trace an Incorrect Exception Address
3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode
3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment
3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address
3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events
3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN
3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
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1. About this Document
This document provides information about known device issues affecting the Intel® Stratix® 10 SX production devices.
Intel® Stratix® 10 SX production devices include:
- Intel® Stratix® 10 SX 2800 L-tile
- Intel® Stratix® 10 SX 2800 H-tile
- Intel® Stratix® 10 SX 2500 L-tile
- Intel® Stratix® 10 SX 2500 H-tile
- Intel® Stratix® 10 SX 2100 H-tile
- Intel® Stratix® 10 SX 1650 H-tile
- Intel® Stratix® 10 SX 1100 H-tile
- Intel® Stratix® 10 SX 850 H-tile
Included in this document are the following:
- Intel-Specific Errata for the Intel® Stratix® 10 SX Devices
- Arm* Cortex*-A53 MPCore* processor and CoreSight* Errata
Note: To obtain third-party IP errata that applies to the HPS and is under NDA, please contact Intel or your local field representative.