Intel® Stratix® 10 SX Device Errata

Download PDF
ID 683399
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Document Revision History for Intel® Stratix® 10 SX Device Errata
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices x
2.1. FPGA 2.2. Device Power Supply, Core, Configuration and I/O 2.3. Hard Processor System
2.2. Device Power Supply, Core, Configuration and I/O x
2.2.1. M20K Simple Quad-Port Mode Support
2.3. Hard Processor System x
2.3.1. HPS Stops on the First Read Request to SDRAM 2.3.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Document Revision History for Intel® Stratix® 10 SX Device Errata

3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing

Description

A Cortex*-A53 MPCore* processor executing a load and store exclusive instruction in a loop is allowed to repeatedly fail under certain conditions. An example of an allowed condition is when another processor repeatedly writes to the same cache line.

Because of this erratum, a non-allocating load from another processor may cause the store-exclusive instruction to repeatedly fail.

The failure occurs under these conditions:
  • One CPU executes a loop containing a load-exclusive and a store-exclusive instruction. The loop continues until the store-exclusive instruction succeeds.
  • Another CPU or master in the system repeatedly executes a load to the same L1 data cache index as the store-exclusive instruction.
  • The cache line containing the address of the load is present in the L1 cache of the CPU, and is not present in the L2 cache.
  • The load does not cause an allocation into the cache of the CPU or the master executing the load. This response results in a snoop arriving at the CPU holding the cache line every time the load is performed.
  • The load is repeated at exactly the same frequency as the load- and store-exclusive loop, such that every time around the loop, the snoop arrives at the same time as the store exclusive instruction is executing.
A load can be non-allocating in Cortex*-A53 MPCore* processor in the following conditions:
  • A load instruction executes on a CPU, while the CPUACTLR.DTAH bit is not set, with one of the following conditions:
    • The memory address is marked as writeback cacheable, with no read allocate, in the page tables.
    • The memory address is marked as writeback cacheable, transient, in the page tables.
    • The memory address is marked as writeback cacheable, and an LDNP non-temporal load instruction is used.
  • A read transaction is made on the ACP interface.

Impact

If a CPU or other master is polling a location to determine when the value changes, then it can prevent another CPU from updating that location, causing a software livelock. Most polling routines, however, use memory that can be allocated into their cache. For improved efficiency it is recommended to use a load-exclusive and WFE instruction to avoid repeated polling. Because the frequency of the polling loop must match the frequency of the load store-exclusive loop, the conditions that cause this erratum are unlikely. Any other disturbance in the system, such as an interrupt or other bus traffic can easily alter the frequency of either loop sufficiently to break the livelock.

Workaround

If the repeating load is being executed on a Cortex*-A53 CPU, then this erratum can be worked around by setting the CPUACTLR.DTAH bit. Note this version of the Cortex*-A53 MPCore* processor sets this bit by default.

If the repeating load is being executed by another master in the system connected to the ACP interface, then the erratum can be worked around by changing the frequency of the polling so that it no longer aligns with the frequency of the load and store exclusive loop.

If the repeating load is being executed by another master in the system connected through the coherent interconnect, then the erratum can be worked around either by ensuring that the other master allocates the line into its cache, or by changing the frequency of the polling so that it no longer aligns with the frequency of the load and store exclusive loop. Note that the Cortex*-A53 MPCore* processor always allocates the line into either the cache or a temporary buffer, and so does not require any workaround for typical polling loops.

Category

Category 3

Level Two Title