Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

1.1. Protocol Signals

The Intel FPGA streaming video protocol allows you to transfer a variety of video data following the AXI4-Stream protocol signals.
Table 1.  Protocol Signals
Signal Description
TDATA

Set TDATA width according to need. The minimum allowable width of TDATA on all IP interfaces is 16 bits. The width of TDATA is byte aligned (i.e. multiple of 8). Systems that require smaller TDATA interfaces must pad their data. The TKEEP and TSTRB signals are unused, so every byte of TDATA is valid (no empty pixels). You deduce the exact length of a video packet from the image dimensions.

TUSER[n:0]

Sized as 1 bit per byte of TDATA.

Strobe TUSER[0] high for the first beat of a frame (or interlaced field) of video and drive low for subsequent packet beats.. For full variants, strobe TUSER[1] for the first beat of a packet to indicate whether it carries control or data information and drive low for subsequent packet beats.. For lite variants, IPs use TUSER[1] for interlaced video to indicate fields of type F1. TUSER[1] must remain high for the remainder of the field. The IP should drive low the other bits of TUSER.
TLAST

The protocol transmits each line of video as one AXI4-S packet. TLAST strobes high to indicate the last beat of the packet. TLAST is always coincident with the last pixel of the line..

TREADY and TVALID Indicate the valid cycles on the bus.
TID The TID data stream identifier is unused.
TDEST The TDEST routing information signal is unused.
TSTRB The TSTRB byte qualifier is unused. All bytes are valid in the protocol.
TKEEP The TKEEP byte qualifier is unused. The protocol has no null bytes.

The TDATA bus carries either pixel data or other information. The TDATA width depends on the color depth, color space, and number of pixels in parallel (PIP).

TDATA byte width is the width of one pixel in bytes multiplied by the number of pixels in parallel.

The width of one pixel, in bytes, is the number of bits per color symbol (BPS) multiplied by the number of color symbols per pixel (SYM), rounded to the next byte. If the width is less than 16 bits, round it to 16 bits.

TDATA byte width = max(2, ceil ((BPS × SYM)/8)) × PIP

The TUSER bus must be TDATA/8 bits wide (and at least 2 bits wide to match the minimum TDATA width of 16 bits).

The TLAST signal indicates the end of a packet.

TDATA, TUSER and TLAST are undefined when TVALID is low.

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