Intel® FPGA Streaming Video Protocol Specification

Download PDF
ID 683397
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

4.2. Full-Raster Start of Frame

The Intel FPGA streaming video full-raster protocol uses a combination of TUSER[0] signal and an embedded sideband start of frame bit field on the TDATA bus, to indicate the position of the start of frame. Where the streaming full-raster interface processes multiple pixels per clock in parallel, the TUSER[0] signal is asserted high for one valid transaction. The start of frame associated with each of the pixels transported on the TDATA bus indicates the exact position of the first pixel on the full raster. The start of frame association is important where it might not be in pixel 1 of the data bus, because of a combination of full-raster data width and the number of pixels in parallel configured on the full-raster interface.
Figure 47. Sync-Timing Mode: Timing Diagram for 1920x1080p at 60 HzThe figure shows CEA-861-D video timing definition for 1920x1080p60, which follows the true start of frame convention.

For most standardized video resolutions the leading edge of the VSYNC pulse coincides with the true start of the frame boundary where video geometry counters are in coordinates (1,1). One exception is where the leading edge of VSYNC is usually offset by a certain amount of video lines, causing the VSYNC to misalign with the actual true start of frame. For instance, 720x240p60 VSYNC pulse is offset by 3 video lines, while 2880x480p60 is offset by 7 video lines. The position of the leading edge of VSYNC relative to the true start of frame location is defined in the relevant standards, such as SMPTE, VESA, and CEA. The full-raster protocol states you assert TUSER[0] at video coordinates (1,1), irrespective of where the actual leading edge of VSYNC occurs.

Figure 48. Sync-Timing Mode: Timing Diagram for 2880x480p at 60 Hz
Level Two Title