Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

4.5. Full-Raster I/O Signals

Table 10.  Full-Raster Transmitter Interface Signals
Signal Name Width Direction Default Value Optional or Required Description
TUSER[0]

As per Intel FPGA streaming video protocol specification.

For TDATA bus, extend the number of color planes by 1, to consider the extra full-raster stream.

Output Low Required Full-raster start of frame. Indicates full-raster true start of frame, i.e., where video geometry counters are in coordinates (0,0), irrespective of where the actual leading edge of VSYNC occurs.
TDATA Output - Required Data payload
TVALID Output - Required Indicates that the transmitter interface is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
TREADY Input - Optional

Indicates that a receiver interface can accept a transfer.

When TREADY is not present in the transmitter interface, it indicates that this interface does not support backpressure.

TLAST Output Low Required Full-raster end of line. Indicates the last pixel of the full-raster line.
Table 11.  Full-Raster Receiver Interface Signals
Signal Name Width Direction Default Value Optional or Required Description
TUSER[0]

As per Intel FPGA streaming video protocol specification.

For TDATA bus, extend the number of color planes by 1, to consider the extra full-raster stream

Input - Required Full-raster start of frame. Indicates full-raster true start of frame, where video geometry counters are in coordinates (0,0), irrespective of where the actual leading edge of VSYNC occurs.
TDATA Input - Required Data payload
TVALID Input - Required Indicates that the transmitter interface is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
TREADY Output High Optional

Indicates that a receiver interface can accept a transfer.

When TREADY is not present in the receiver interface, indicates that this interface can always accept a transfer.

TLAST Input - Required Full raster end of line. Indicates the last pixel of the full-raster line.
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