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2.2.1. TDATA Pixel Packing
2.2.2. RGB Pixel Packing
2.2.3. YCbCr 444 Pixel Packing
2.2.4. YCbCr 422 Pixel Packing
2.2.5. YCbCr 420 Pixel Packing
2.2.6. Four-Channel Video Pixel Packing
2.2.7. Packing with Multiple Pixels in Parallel
2.2.8. Multiple Pixels in Parallel and Empty Pixels
2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel
2.2.10. Packing RGB444 onto an RGB888 Interface
2.2.11. Packing with Less than 8 bits per Symbol Natively
2.2.12. Interlaced Fields
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4. Intel FPGA Streaming Video Full-Raster Protocol
The full-raster protocol adds clocked video data to the lite variant of the Intel FPGA streaming video I/O.
Sometimes the off-screen parts of video frames are irrelevant. For most cases the streaming video protocol only preserves active video data and filters out all off-screen data. However, these areas of blanking may carry significant amounts of side-band data, such as audio, timestamps, HDR (High Dynamic Range) information, and any other metadata related to a specific video protocol.
Figure 44. Mapping video data and timing markers from clocked video to Intel FPGA streaming full-raster protocol
The figure shows how the full-raster protocol supports full-raster video on the lite variant of the Intel FPGA streaming video protocol. Video timing markers are traditionally explicitly exposed as part of a clocked video I/O interface (e.g., DE, Field, Vsync/ Vblank, and Hsync/ Hblank). The full-raster protocol takes video timing data markers and embeds them at the top of the TDATA payload of an Intel FPGA streaming video protocol, to allow for distribution and processing of full-raster video formats.
Embedding full-raster data into the lite variant of the Intel FPGA streaming video protocol means that you can use AMBA AXI4-Stream agnostic IPs to move, capture, or generate full-raster data. For example, cross-points, video switch, DMA engines, PCI-Express transfer, Ethernet transcoding. None of these IPs need to know the content in the TDATA stream, they just need to move it.