Qsys System Design Tutorial

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ID 683378
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Qsys System Design Tutorial
1. Qsys System Design Tutorial x
1.1. Software and Hardware Requirements 1.2. Download and Install the Tutorial Design Files 1.3. Open the Tutorial Project 1.4. Creating Qsys Systems 1.5. Assemble a Hierarchical System 1.6. Viewing the Memory Tester System in Qsys 1.7. Compiling and Downloading Software to a Development Board 1.8. Debugging Your Design 1.9. Verifying Hardware in System Console 1.10. Simulating Custom Components 1.11. View a Diagram of the Completed System
1.4. Creating Qsys Systems x
1.4.1. Create a Data Pattern Generator Qsys System 1.4.2. Create a Data Pattern Checker Qsys System
1.4.1. Create a Data Pattern Generator Qsys System x
1.4.1.1. Create a New Qsys System and Set up the Clock Source 1.4.1.2. Add a Pipeline Bridge 1.4.1.3. Add a Custom Pattern Generator 1.4.1.4. Add a PRBS Pattern Generator 1.4.1.5. Add a Two-to-One Streaming Multiplexer 1.4.1.6. Verify the Memory Address Map 1.4.1.7. Connect the Reset Signals 1.4.1.8. Save the System
1.4.2. Create a Data Pattern Checker Qsys System x
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource 1.4.2.2. Add a Pipeline Bridge 1.4.2.3. Add a Custom Pattern Checker 1.4.2.4. Add the PRBS Pattern Checker 1.4.2.5. Add a One-to-Two Streaming Demultiplexer 1.4.2.6. Verify the Memory Address Map 1.4.2.7. Connect the Reset Signals 1.4.2.8. Save the System
1.5. Assemble a Hierarchical System x
1.5.1. Create the Hierarchical Memory Tester System 1.5.2. Complete the Top-Level System
1.5.1. Create the Hierarchical Memory Tester System x
1.5.1.1. Add the Pattern Generator 1.5.1.2. Add the Pattern Checker 1.5.1.3. Add Memory Master Components 1.5.1.4. Connect the Reset Signals 1.5.1.5. Verify the Memory Address Map 1.5.1.6. Save the System
1.5.1.3. Add Memory Master Components x
1.5.1.3.1. Add a Pattern Writer Component 1.5.1.3.2. Add a Pattern Reader Component 1.5.1.3.3. Add a RAM Test Controller
1.9. Verifying Hardware in System Console x
1.9.1. Open the Tutorial Project 1.9.2. Add the JTAG-to-Avalon Master Bridge 1.9.3. Debug with System Console
1.10. Simulating Custom Components x
1.10.1. Generate a Testbench System in Qsys 1.10.2. Run Simulation In the ModelSim-Altera Software
1.10.1. Generate a Testbench System in Qsys x
1.10.1.1. Create a New Qsys System for the Design Under Test 1.10.1.2. Export Design Under Test 1.10.1.3. Generate a Testbench System 1.10.1.4. Generate Testbench System's Simulation Models
1.10.2. Run Simulation In the ModelSim-Altera Software x
1.10.2.1. Set Up the Simulation Environment 1.10.2.2. Run the Simulation
1. Qsys System Design Tutorial

1.8. Debugging Your Design

If the memory test starts but does not complete successfully, the terminal displays failure messages. If you see failure messages from the memory test, review the previous sections and check that you have completed all of the instructions in this tutorial successfully. A missed connection or incorrect memory address assignment may cause the tester design to fail on the board.

Altera provides completed systems, so that you can verify your system designs. You can copy the completed systems into the project directory with different names, so that you can open two different instances of Qsys for a side-by-side comparison. Alternatively, you can replace your systems with the provided completed systems to run the memory tester design successfully.

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