Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

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ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

1.2. Supported IP Cores and Devices

Table 1.  Ethernet Link Inspector Supported IP Cores for Intel® Stratix® 10 L-, H-, and E-tile Devices
Device IP Core Data Rate (Gbps) IP Type Auto Negotiation and Link Training 1 FEC 1 Link Monitor Link Analysis
Intel® Stratix® 10 L-tile 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP 10 Soft Yes Fire code

(2112,2080)

 Yes Yes
25G Ethernet Intel® FPGA IP 25 Soft N/A RS-FEC

(528,514)

 Yes N/A
Low Latency 40G Ethernet Intel® FPGA IP 40 Soft Yes Fire code

(2112,2080)

 Yes Yes
Low Latency 100G Ethernet Intel® FPGA IP 100 Soft Yes RS-FEC

(528,514)

 Yes Yes
Intel® Stratix® 10 H-tile 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP 10 Soft Yes Fire code

(2112,2080)

 Yes Yes
25G Ethernet Intel® FPGA IP 25 Soft N/A RS-FEC

(528,514)

 Yes N/A
Low Latency 40G Ethernet Intel® FPGA IP 40 Soft Yes Fire code

(2112,2080)

 Yes Yes
Low Latency 100G Ethernet Intel® FPGA IP 100 Soft Yes RS-FEC

(528,514)

 Yes Yes
H-tile Hard IP for Ethernet Intel® FPGA IP 50 Hard Yes N/A Yes Yes
100 Hard Yes N/A Yes Yes
Intel® Stratix® 10 E-tile E-tile Hard IP for Ethernet Intel® FPGA IP 10 Hard Yes N/A Yes N/A
25 Hard Yes RS-FEC

(528,514)

 Yes N/A
100

(25Gx4 - NRZ)

 Hard Yes RS-FEC

(528,514)

 Yes N/A
100

(50Gx2 - PAM4)

 Hard Yes RS-FEC

(544,514)

 Yes N/A
1 Feature details here shows support model for the IP and not the Ethernet Link Inspector support.
Level Two Title