Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

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ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

3.2.2.1. Sequencer State Machine Tab

The Sequencer State Machine (SSM) tab shows the flow of sequencer state machine states that the device goes through in the specific Signal Tap capture for the selected Ethernet IP core.
Figure 7. Example of Sequencer State Machine Tab GUI
Note: SSM State names in below image is for 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP core. Based on the Ethernet IP, these state names may vary. Refer to Table 4 for details on state names specific to the IP.
Table 5.  Sequencer State Machine Tab Parameters
Parameter Description
Assumed Reference Timer Clock Shows the assumed value of the clock frequency driving the reference timer. Ensure that the value of this clock is the same as the clock frequency configured in the Platform Designer window of the selected Ethernet IP core.
Note: If the assumed value of the clock frequency does not match the clock frequency in Platform Designer window of the selected IP core, the timer values displayed in Link Analysis GUI will be incorrect. For example, the Timer values reported in Start, Stop and Delta columns in the Sequencer State machine tab would be incorrect.
States Shows the flow of SSM states (from SEQ_Initialize to Data modes) that the device goes through in a specific capture. A successful state completion is highlighted in green whereas a state completion failure is highlighted in red.
Start Timestamp for start time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM started.
Stop Timestamp for stop time. Shows the reference timer value (in millisecond) corresponding to a specific state of SSM finished.
Delta Timestamp for delta time. Shows the total time spent (in millisecond) on a specific state of SSM.
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