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Answers to Top FAQs
1. Intel® Hyperflex™ FPGA Architecture Introduction
2. Intel® Hyperflex™ Architecture RTL Design Guidelines
3. Compiling Intel® Hyperflex™ Architecture Designs
4. Design Example Walk-Through
5. Retiming Restrictions and Workarounds
6. Optimization Example
7. Intel® Hyperflex™ Architecture Porting Guidelines
8. Appendices
9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive
10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History
2.4.2.1. High-Speed Clock Domains
2.4.2.2. Restructuring Loops
2.4.2.3. Control Signal Backpressure
2.4.2.4. Flow Control with FIFO Status Signals
2.4.2.5. Flow Control with Skid Buffers
2.4.2.6. Read-Modify-Write Memory
2.4.2.7. Counters and Accumulators
2.4.2.8. State Machines
2.4.2.9. Memory
2.4.2.10. DSP Blocks
2.4.2.11. General Logic
2.4.2.12. Modulus and Division
2.4.2.13. Resets
2.4.2.14. Hardware Re-use
2.4.2.15. Algorithmic Requirements
2.4.2.16. FIFOs
2.4.2.17. Ternary Adders
5.2.1. Insufficient Registers
5.2.2. Short Path/Long Path
5.2.3. Fast Forward Limit
5.2.4. Loops
5.2.5. One Critical Chain per Clock Domain
5.2.6. Critical Chains in Related Clock Groups
5.2.7. Complex Critical Chains
5.2.8. Extend to locatable node
5.2.9. Domain Boundary Entry and Domain Boundary Exit
5.2.10. Critical Chains with Dual Clock Memories
5.2.11. Critical Chain Bits and Buses
5.2.12. Delay Lines
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1.1. Intel® Hyperflex™ Architecture Design Concepts
Term/Phrase | Description |
---|---|
Critical Chain | Any design condition that prevents retiming of registers. The limiting factor can include multiple register-to-register paths in a chain. The fMAX of the critical chain and its associated clock domain is limited by the average delay of a register-to-register path, and quantization delays of indivisible circuit elements like routing wires. Use Fast Forward compilation to break critical chains. |
Fast Forward Compilation | Generates design-specific timing closure recommendations, and forward-looking performance results after removal of each timing restriction. |
Hyper-Aware Design Flow | Design flow that enables the highest performance in Intel® Hyperflex™ architecture FPGAs through Hyper-Retiming, Hyper-Pipelining, Fast Forward compilation, and Hyper-Optimization. |
Intel® Hyperflex™ FPGA Architecture | Device core architecture that includes additional registers, called Hyper-Registers, everywhere throughout the core fabric. Hyper-Registers provide increased bandwidth and improved area and power efficiency. |
Hyper-Optimization | Design process that improves design performance through implementation of key RTL changes recommended by Fast Forward compilation, such as restructuring logic to use functionally equivalent feed-forward or pre-compute paths, rather than long combinatorial feedback paths. |
Hyper-Pipelining | Design process that eliminates long routing delays by adding additional pipeline stages in the interconnect between the ALM registers. This technique allows the design to run at a faster clock frequency. |
Hyper-Retiming | During Fast Forward compile, Hyper-Retiming speculatively removes signals from registers to enable mobility in the netlist for retiming. |
Multiple Corner Timing Analysis | Analysis of multiple "timing corner cases" to verify your design's voltage, process, and temperature operating conditions. Fast-corner analysis assumes best-case timing conditions. |