Visible to Intel only — GUID: jka1465342700783
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Generating the Partial Reconfiguration Flow Script
Step 8: Running the Partial Reconfiguration Flow Script
Step 9: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: jka1465342700783
Ixiasoft
Updating the Top-Level Design
To update the top.sv file with the PR_IP instance:
- To add the pr_ip instance to the top-level design, uncomment the following code block in top.sv file:
pr_ip u_pr_ip ( .clk (clock), .nreset (1'b1), .freeze (freeze), .pr_start (1'b0), // ignored for JTAG .status (pr_ip_status), .data (16'b0), .data_valid (1'b0), .data_ready () );
- To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. Uncomment the following lines of code:
assign led_two_on_w = freeze ? 1'b1 : pr_led_two_on; assign led_three_on_w = freeze ? 1'b1 : pr_led_three_on;
- To assign an instance of the default persona (blinking_led), update the top.sv file with the following block of code:
blinking_led u_blinking_led ( .led_two_on (pr_led_two_on), .led_three_on (pr_led_three_on), .clock (clock), .counter (count_d) );
Figure 8. Partial Reconfiguration IP Core Integration