AN 770: Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

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ID 683345
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 5: Defining Personas Step 6: Creating Revisions Step 7: Generating the Partial Reconfiguration Flow Script Step 8: Running the Partial Reconfiguration Flow Script Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 6: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

Document Revision History

Table 5.  Document Revision History
Date Version Changes

2017.11.06

17.1.0
  • Updated the Reference Design Requirements section with software version
  • Updated the Flat Reference Design without PR Partitioning figure with design block changes
  • Updated the Reference Design Files table with information on the Top_counter.sv module
  • Updated the Partial Reconfiguration IP Core Integration figure with design block changes
  • Updated the figures - Design Partitions Window and Logic Lock Regions Window to reflect the new GUI
  • Text edits

2017.05.08

17.0.0
  • Updated software version in Reference Design Requirements section
  • Added information about enable freeze interface option in Step 4: Adding the Partial Reconfiguration IP Core section
  • Added information on the importance of SDC ordering in Step 4: Adding the Partial Reconfiguration IP Core section
  • Added an overview on base, synthesis, and implementation revisions in Step 6: Creating Revisions section
  • Text edits

2016.10.31

16.1.0
  • Updated flow with 16.1 PR specific GUI features:
    • Design Partitions Window updates
    • Logic Lock region updates
    • Revision and Revision Types updates
  • New topic added for modifying an existing persona
  • New topic added for including a persona in the design

2016.07.07

16.0.0

Initial release of the document
Level Two Title