AN 770: Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

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ID 683345
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 5: Defining Personas Step 6: Creating Revisions Step 7: Generating the Partial Reconfiguration Flow Script Step 8: Running the Partial Reconfiguration Flow Script Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 6: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Partially Reconfiguring a Design on Intel® Arria® 10 SoC Development Board

Step 4: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core

The Intel® Arria® 10 Partial Reconfiguration Controller IP core enables reconfiguration of the PR partition. This IP core uses JTAG to reconfigure the PR partition. To add the Intel® Arria® 10 Partial Reconfiguration Controller IP core to your Intel® Quartus® Prime project:
  1. Type Partial Reconfiguration in the IP Catalog (Tools > IP Catalog).
  2. Double-click the Intel® Arria® 10 Partial Reconfiguration Controller IP core.
  3. In the Create IP Variant dialog box, type pr_ip as the file name, and then click Create. Use the default parameterization for pr_ip. Ensure that the Enable JTAG debug mode and Enable freeze interface options are turned on, and Enable Avalon-MM slave interface option is turned off.
    Figure 7.  Intel® Arria® 10 Partial Reconfiguration Controller IP Core Parameters
  4. Click Finish, and exit the parameter editor without generating the system. The parameter editor generates the pr_ip.ip IP variation file and adds the file to the blinking_led project.
    Note:
    1. If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the following line:
      set_global_assignment -name IP_FILE pr_ip.ip
    2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration Controller IP core.
      Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files that you use to create these clocks in the .qsf file for your Intel® Quartus® Prime project revision. For more information, refer to the Partial Reconfiguration IP Solutions User Guide.
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