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Ixiasoft
1.1. System Architecture
The reference designs demonstrate fully operational subsystems that integrate the Triple-Speed Ethernet IP core for Ethernet applications.
Figure 1. Reference Design with SGMII Interface—Arria 10 DevicesThe figure shows a high-level block diagram of the reference design implementing the SGMII interface with Arria 10 devices.
Figure 2. Reference Design with SGMII Interface—Stratix V GX DevicesThe figure shows a high-level block diagram of the reference design implementing the SGMII interface with Stratix V GX devices.
Figure 3. Reference Design with RGMII Interface—Arria V GX and Cyclone V GX DevicesThe figure shows a high-level block diagram of the reference design implementing the RGMII interface with Arria V GX and Cyclone V GX devices.