• This IP core generates a 125-MHz PLL output clock (clk_125M).
• This output clock is the system-wide clock source for the Qsys system.
• All the components in these reference designs use the 125-MHz clock from the PLL core.

• This IP core provides a connection between the System Console and Qsys system through the physical interfaces.
• The System Console can initiate Avalon Memory-Mapped (Avalon-MM) transactions by sending encoded streams of bytes through the bridge’s physical interfaces.

• This IP core provides an integrated Ethernet MAC, PCS, and PMA solution for Ethernet applications.
• The Triple Speed Ethernet IP core transmits Ethernet packets from Avalon Streaming (Avalon-ST) interface to a 1.25-Gbps serial transceiver interface and receives packets from the opposite direction.

This Qsys custom component generates Ethernet packets.

Refer to Ethernet Packet Generator for more information.

This Qsys custom component verifies the payload of all receive packets, indicates the validity of the packets, and collects statistics about each packet, such as the number of bytes received.

Refer to Ethernet Packet Monitor for more information.

• This Qsys custom component connects mismatched Avalon-ST source and sink interfaces.
• The adapter allows you to connect a data source to a data sink of differing byte sizes. For TX-to-RX Avalon-ST reverse loopback in these design examples, ff_tx_err is a 1-bit error signal and rx_err is a 6-bit error signal. The adapter ensures that the per-bit error information provided by ff_tx_err at the source interface connects correctly to the rx_err signal.
• The adapter connects matching error conditions that are handled by the source and the sink.

• This Qsys custom component accepts data on its two Avalon-ST sink interfaces and multiplexes the data for transmission on its Avalon-ST source interface.
• One Avalon-ST sink interface connects to the source of the Ethernet Packet Generator for forward loopback while the other sink interface connects to the source of the Error Adapter for reverse loopback.
• The Avalon-ST source interface sends Ethernet packets to the Triple-Speed Ethernet IP Core.

• This Qsys custom component accepts data on its Avalon-ST sink interface and splits the data for transmission on its two Avalon-ST source interfaces.
• The Avalon-ST sink interface receives Ethernet packets from the Triple-Speed Ethernet IP Core. One Avalon-ST source interface connects to the sink of the Ethernet Packet Generator for forward loopback while the other source interface connects to the sink of the Error Adapter for reverse loopback.