AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

1.4.3. Avalon-ST Reverse Loopback Test

Complete the tasks to run the Avalon-ST reverse loopback test.
Set up the development board. The Avalon-ST reverse loopback test requires an external Ethernet packet generator.
  1. Using the Ethernet cable assembly, connect the external generator to the RJ-45 port of the FPGA development board.
  2. Connect the programming cable to the JTAG connection port.
  3. Connect the board to the power supply input (J4).
To run the internal MAC loopback test:
  1. Set up the System Console.
    1. Open Qsys.
    2. On the Tools menu, click System Console.
      The System Console is a debugging tool that provides you with Tcl scripts to perform low-level hardware debugging and run tests on your reference designs. The console communicates to the hardware components instantiated into your Qsys system reference designs through the JTAG to Avalon Master Bridge.
  2. Open the config.tcl script and set LOOP_ENA to 0 to disable the MAC loopback mode.
    For more information, refer to Configuration Script.
  3. Type the following command to start the MAC and PHY configurations in the System Console:
    source config.tcl
    The System Console displays the copper link connection status and the PHY’s operating speed and mode. Verify that the console displays the correct configurations
  4. Start sending Ethernet packets from the external packet generator to the FPGA development board and verify that the packets are correctly looped back to the external packet generator.
  5. Type the following command to view the MAC statistic counters:
    source tse_stat_read.tcl
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