AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

ID 683344
Date 12/14/2015
Public

1.2. Interface Signals

The top-level signals of the reference designs show the behavior of the specific operations.

Clock and Reset Signals

Table 4.  RGMII Clock and Reset Signals
Signal Description
clk_clk Reference design clock. The clock is derived from the PLL.
triple_speed_ethernet_0_pcs_mac_rx_clock_connection_clk RGMII receive clock. The clock is sourced from the on-board PHY chip.
triple_speed_ethernet_0_pcs_mac_tx_clock_connection_clk RGMII transmit clock. The clock is sourced from the clock multiplexer which is sourced from the PLL.
reset_reset_n Single reset signal for all logic in the reference design.
Table 5.  SGMII Clock and Reset Signals
Signal Description
clk_clk Reference design clock. The clock is derived from the PLL.
triple_speed_ethernet_0_pcs_ref_clk_clock_connection_clk Reference clock for the transceiver. The clock is sourced from the 125-MHz oscillator.
reset_reset_n Single reset signal for all logic in the reference design. Connect this reset signal to the RESET push button (USER_PB0).

Triple-Speed Ethernet Component Signals

Table 6.  RGMII Reference Design Signals
Signal Description
triple_speed_ethernet_0_mac_rgmii_connection_rgmii_in RGMII receive data bus. Connect this bus to the on-board PHY chip.
triple_speed_ethernet_0_mac_rgmii_connection_rx_control RGMII receive control output signal. Connect this signal to the on-board PHY chip.
triple_speed_ethernet_0_mac_rgmii_connection_rgmii_out RGMII transmit data bus. Connect this bus to the on-board PHY chip.
triple_speed_ethernet_0_mac_rgmii_connection_tx_control RGMII transmit control output signal. Connect this signal to the on-board PHY chip.
Table 7.  SGMII Reference Design Signals
Signal Description
triple_speed_ethernet_0_serial_connection_rxp_0 SGMII receive serial data bus. Connect this bus to the on-board PHY chip.
triple_speed_ethernet_0_serial_connection_txp_0 SGMII transmit serial data bus. Connect this bus to the on-board PHY chip.