1.4. Running the Reference Designs
When the board is set up and the FPGA is configured, you can start running the design tests.
To run the tests, download and unzip the reference design files to your local directory.
| Components | File | Description |
|---|---|---|
| Top Level Design File | top.v | Top-level entity file of the reference design for verification in the hardware. |
| top_out.sdc | Intel® Quartus® Prime SDC constraint file for use with the TimeQuest timing analyzer. | |
| qsys_top.qsys | Qsys file of the reference design. | |
| pll.v | The IP-generated PLL file. | |
| Ethernet Generator | eth_gen_hw.tcl | Qsys custom component which generates Ethernet packets. |
| eth_gen.v | The top level file of the Ethernet Packet Generator. | |
| prbs23.v | Module to generate Pseudo-Random Bit Sequence 23 data. | |
| shiftreg_data.v | RAM-based shift register to delay transmit packet payload sending to Triple-Speed Ethernet TX FIFO interface for CRC checksum merging at EOP. | |
| shiftreg_ctrl.v | RAM-based shift register to store and delay control signals. | |
| crcgen_dat32.v | Module to generate checksum CRC32. | |
| Ethernet Monitor | eth_mon_hw.cl | Qsys custom component which verifies the payload of all receive packets. |
| eth_mon.v | Top level file of the Ethernet Packet Monitor. | |
| crcchk_dat32.v | Module to verify the data payload of the received packets. | |
| CRC Generator/Checke | crc32.sdc | Intel® Quartus® Prime SDC constraint file for use with the TimeQuest timing analyzer. |
| crc32_chk.v | Top level file of the CRC 32 checker. | |
| crc32_gen.v | Top level file of the CRC 32 generator. | |
| avalon_st_to_crc_if_bridge.v | Module to convert the Avalon-ST signal to the CRC 32 calculator input signal. | |
| byte_endian_converter.v | Module to convert the input data byte to big or little endian. | |
| crc32_calculator.v | Module to calculate the crc32 checksum for the incoming data. | |
| crc_checksum_aligner.v | Module to align the checksum with crc_valid signal. | |
| crc_comparator | Module to compare the checksum of the receiving packet with the Ethernet CRC 32 residue value. | |
| Avalon-St Multiplexer (not applicable for Arria 10 designs) |
st_mux_2_to_1_hw.tcl | The Qsys custom component accepts data on its two Avalon-ST sink interfaces, and multiplexes the data for transmission on its Avalon-St source interface. |
| st_mux_2_to_1.v | ||
| st_mux.v | LPM_MUX IP core file. | |
| Avalon St-Splitter (not applicable for Arria 10 designs) |
aso_splitter_hw.tcl | The Qsys custom component accepts data on its Avalon-ST sink interface and splits the data for transmission on its two Avalon-ST source interfaces. |
| aso_splitter.v | ||
| Error Adaptor (not applicable for Arria 10 designs) |
error_adapter2_hw.tcl | The Qsys custom component connects mismatched Avalon-ST source and sink interfaces. |
| error_adapter2.tcl |