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1. Intel® FPGA SDK for OpenCL™ Standard Edition Overview
2. Intel® FPGA SDK for OpenCL™ Offline Compiler Kernel Compilation Flows
3. Obtaining General Information on Software, Compiler, and Custom Platform
4. Managing an FPGA Board
5. Structuring Your OpenCL Kernel
6. Designing Your Host Application
7. Compiling Your OpenCL Kernel
8. Emulating and Debugging Your OpenCL Kernel
9. Reviewing Your Kernel's report.html File
10. Profiling Your OpenCL Kernel
11. Developing OpenCL™ Applications Using Intel® Code Builder for OpenCL™
12. Intel® FPGA SDK for OpenCL™ Standard Edition Advanced Features
A. Support Statuses of OpenCL Features
B. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide
3.1. Displaying the Software Version (version)
3.2. Displaying the Compiler Version (-version)
3.3. Listing the Intel® FPGA SDK for OpenCL™ Standard Edition Utility Command Options (help)
3.4. Listing the Intel® FPGA SDK for OpenCL™ Offline Compiler Command Options (no argument, -help, or -h)
3.5. Listing the Available FPGA Boards in Your Custom Platform (-list-boards)
3.6. Displaying the Compilation Environment of an OpenCL Binary (env)
4.1. Installing an FPGA Board (install)
4.2. Uninstalling the FPGA Board (uninstall)
4.3. Querying the Device Name of Your FPGA Board (diagnose)
4.4. Running a Board Diagnostic Test (diagnose <device_name>)
4.5. Programming the FPGA Offline or without a Host (program <device_name>)
4.6. Programming the Flash Memory (flash <device_name>)
5.1. Guidelines for Naming the Kernel
5.2. Programming Strategies for Optimizing Data Processing Efficiency
5.3. Programming Strategies for Optimizing Pointer-to-Local Memory Size
5.4. Implementing the Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension
5.5. Implementing OpenCL Pipes
5.6. Implementing Arbitrary Precision Integers
5.7. Using Predefined Preprocessor Macros in Conditional Compilation
5.8. Declaring __constant Address Space Qualifiers
5.9. Including Structure Data Types as Arguments in OpenCL Kernels
5.10. Inferring a Register
5.11. Enabling Double Precision Floating-Point Operations
5.12. Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
5.4.1. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension
5.4.2. Channel Data Behavior
5.4.3. Multiple Work-Item Ordering for Channels
5.4.4. Restrictions in the Implementation of Intel® FPGA SDK for OpenCL™ Standard Edition Channels Extension
5.4.5. Enabling the Intel® FPGA SDK for OpenCL™ Standard Edition Channels for OpenCL Kernel
5.4.5.1. Declaring the Channel Handle
5.4.5.2. Implementing Blocking Channel Writes
5.4.5.3. Implementing Blocking Channel Reads
5.4.5.4. Implementing I/O Channels Using the io Channels Attribute
5.4.5.5. Emulating I/O Channels
5.4.5.6. Use Models of Intel® FPGA SDK for OpenCL™ Standard Edition Channels Implementation
5.4.5.7. Implementing Buffered Channels Using the depth Channels Attribute
5.4.5.8. Enforcing the Order of Channel Calls
5.5.5.1. Ensuring Compatibility with Other OpenCL SDKs
5.5.5.2. Declaring the Pipe Handle
5.5.5.3. Implementing Pipe Writes
5.5.5.4. Implementing Pipe Reads
5.5.5.5. Implementing Buffered Pipes Using the depth Attribute
5.5.5.6. Implementing I/O Pipes Using the io Attribute
5.5.5.7. Enforcing the Order of Pipe Calls
6.1. Host Programming Requirements
6.2. Allocating OpenCL Buffers for Manual Partitioning of Global Memory
6.3. Collecting Profile Data During Kernel Execution
6.4. Accessing Custom Platform-Specific Functions
6.5. Modifying Host Program for Structure Parameter Conversion
6.6. Managing Host Application
6.7. Allocating Shared Memory for OpenCL Kernels Targeting SoCs
6.8. Debugging Your OpenCL System That is Gradually Slowing Down
6.6.1. Displaying Example Makefile Fragments (example-makefile or makefile)
6.6.2. Compiling and Linking Your Host Application
6.6.3. Linking Your Host Application to the Khronos ICD Loader Library
6.6.4. Programming an FPGA via the Host
6.6.5. Termination of the Runtime Environment and Error Recovery
6.6.2.1. Displaying Flags for Compiling Host Application (compile-config)
6.6.2.2. Displaying Paths to OpenCL Host Runtime and MMD Libraries (ldflags)
6.6.2.3. Listing OpenCL Host Runtime and MMD Libraries (ldlibs)
6.6.2.4. Displaying Information on OpenCL Host Runtime and MMD Libraries (link-config or linkflags)
7.1. Compiling Your Kernel to Create Hardware Configuration File
7.2. Compiling Your Kernel without Building Hardware (-c)
7.3. Specifying the Location of Header Files (-I=<directory>)
7.4. Specifying the Name of an Intel® FPGA SDK for OpenCL™ Offline Compiler Output File (-o=<filename>)
7.5. Compiling a Kernel for a Specific FPGA Board (-board=<board_name>)
7.6. Resolving Hardware Generation Fitting Errors during Kernel Compilation (-high-effort)
7.7. Defining Preprocessor Macros to Specify Kernel Parameters (-D<macro_name>)
7.8. Generating Compilation Progress Report (-v)
7.9. Displaying the Estimated Resource Usage Summary On-Screen (-report)
7.10. Suppressing Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler (-W)
7.11. Converting Warning Messages from the Intel® FPGA SDK for OpenCL™ Offline Compiler into Error Messages (-Werror)
7.12. Removing Debug Data from Compiler Reports and Source Code from the .aocx File (-g0)
7.13. Disabling Burst-Interleaving of Global Memory (-no-interleaving=<global_memory_type>)
7.14. Configuring Constant Memory Cache Size (-const-cache-bytes=<N>)
7.15. Relaxing the Order of Floating-Point Operations (-fp-relaxed)
7.16. Reducing Floating-Point Rounding Operations (-fpc)
8.1. Modifying Channels Kernel Code for Emulation
8.2. Compiling a Kernel for Emulation (-march=emulator)
8.3. Emulating Your OpenCL Kernel
8.4. Debugging Your OpenCL Kernel on Linux
8.5. Limitations of the Intel® FPGA SDK for OpenCL™ Standard Edition Emulator
8.6. Discrepancies in Hardware and Emulator Results
12.1.1. Understanding RTL Modules and the OpenCL Pipeline
12.1.2. Packaging an OpenCL Helper Function File for an OpenCL Library
12.1.3. Packaging an RTL Component for an OpenCL Library
12.1.4. Verifying the RTL Modules
12.1.5. Packaging Multiple Object Files into a Library File
12.1.6. Specifying an OpenCL Library when Compiling an OpenCL Kernel
12.1.7. Using an OpenCL Library that Works with Simple Functions (Example 1)
12.1.8. Using an OpenCL Library that Works with External Memory (Example 2)
12.1.9. OpenCL Library Command-Line Options
12.1.1.1. Overview: Intel FPGA SDK for OpenCL Pipeline Approach
12.1.1.2. Integration of an RTL Module into the Intel FPGA SDK for OpenCL Pipeline
12.1.1.3. Stall-Free RTL
12.1.1.4. RTL Module Interfaces
12.1.1.5. Avalon Streaming (Avalon-ST) Interface
12.1.1.6. RTL Reset and Clock Signals
12.1.1.7. XML Syntax of an RTL Module
12.1.1.8. Interaction between RTL Module and External Memory
12.1.1.9. Order of Threads Entering an RTL Module
12.1.1.10. OpenCL C Model of an RTL Module
12.1.1.11. Potential Incompatibility between RTL Modules and Partial Reconfiguration
A.1.1. OpenCL1.0 C Programming Language Implementation
A.1.2. OpenCL C Programming Language Restrictions
A.1.3. Argument Types for Built-in Geometric Functions
A.1.4. Numerical Compliance Implementation
A.1.5. Image Addressing and Filtering Implementation
A.1.6. Atomic Functions
A.1.7. Embedded Profile Implementation
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6.1.3. Multiple Host Threads
The Intel® FPGA SDK for OpenCL™ host library is thread-safe.
All OpenCL APIs are thread safe except the clSetKernelArg function.
It is safe to call clSetKernelArg from any host thread or in a reentrant way as long as concurrent calls to clSetKernelArg operate on different cl_kernel objects.
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