Visible to Intel only — GUID: btf1521056620309
Ixiasoft
Visible to Intel only — GUID: btf1521056620309
Ixiasoft
12.1.1.5. Avalon Streaming (Avalon-ST) Interface
The offline compiler expects the RTL module to support Avalon-ST interface with readyLatency = 0, at both input and output.
- ivalid and iready, as the input Avalon-ST interface
- ovalid and oready, as the output Avalon-ST interface
For an RTL module with a fixed latency, the output signals (ovalid and oready) can have constant high values, and the input ready signal (iready) can be ignored.
A stall-free RTL module might receive an invalid input signal (ivalid is low). In this case, the module ignores the input and produces invalid data on the output. For a stall-free RTL module without an internal state, it might be easier to propagate the invalid input through the module. However, for an RTL module with an internal state, you must handle an ivalid = 0 input carefully.