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1. Quick Start Guide
2. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Intel® Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: bhc1411112947408
Ixiasoft
2. Detailed Description for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
This design example demonstrates the functionality of data streaming using standard clocking mode.
To generate the design example, select any of the following presets:
- Standard Clocking Mode 2x25.0G
- Standard Clocking Mode 4x28.0G
- Standard Clocking Mode 6x12.5G
- Standard Clocking Mode 6x17.4G
Note: By default, the design examples are generated as duplex core. To generate the design examples in simplex core, select Simplex for the Direction parameter.