Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1. Features

Features for Advanced Clocking Mode design example includes:
  • Support up to 16 lanes for 17.4 Gbps and 4 lanes for 28 Gbps transceiver data rate
  • Support for duplex transmission modes
  • Traffic checker for data verification and lane de-skew verification
  • Support for CRC error injection using Nios® II processor
  • Slave test mode for master and slave testing